Semiconductor memory card, semiconductor memory control apparatus, and semiconductor memory control method

ABSTRACT

A host information memory is provided in a semiconductor memory card and a data write start address and a data size supplied by an access unit are stored. A free physical area generation section determines whether or not to perform erasing of an invalid block of a nonvolatile memory when writing of data based on the data write start address and data size, and determines the number of blocks to be erased. When erasing, writing of data and erasing of invalid blocks are simultaneously performed with respect to different memory chips. Erase process of data, herewith, can be optimized and high speed access from the access unit to a semiconductor memory card can be realized.

TECHNICAL FIELD

The present invention relates to a semiconductor memory card, asemiconductor memory control apparatus, and a semiconductor memorycontrol method.

BACKGROUND ART

Various kinds of recording media for recording digital data such asmusic contents and visual data are there, such as magnetic disks,optical disks, and magnetic optical disks. A semiconductor memory card,which is one type of such recording media, uses a semiconductor memorysuch as a flash ROM (Read Only Memory) as a recording element and makesit possible to reduce a size of a recording medium; therefore,semiconductor memory card is rapidly spreading with a focus on smallsize mobile apparatuses, such as digital still cameras and mobiletelephone terminals.

Since data stored in a semiconductor memory card are managed by a filesystem, users can easily treat the stored data as a file. There is a FATfile system, used as a conventional file system, disclosed inISO/IEC9293, “Information Technology-Volume and file structure of diskcartridges for information”, 1994. In addition, there are UDF (UniversalDisk Format), NTFS (New Technology File System), and the like describedin OSTA Universal Disk Format Specification Revision 1.50, 1997. Thesemiconductor memory card with data managed by such file systems canshare a file between apparatuses that interpret the same file system;therefore, data can be given/received between apparatuses.

There has been a problem in that the file system needs to perform atwo-stage operation in which data is first erased in rewriting data andthereafter data is written, resulting in much time consumed untilfinishing writing completely.

As a method for solving such a problem, for example, a semiconductorstorage device disclosed in Japanese Unexamined Patent Publication No.11-191297 is heretofore known. The present invention has a plurality ofnonvolatile memories, performs erasing in a second nonvolatile memorywhen performing writing in a first nonvolatile memory, and performsrewriting data in a short time by processing them in parallel. However,in this conventional technology, the erase process is performed inparallel regardless of the data size to be written in a memory chip. Forexample, in a NAND type flash memory, time for erasing one erase block(normally, 16 KB) is to be 2.0 mSec. Accordingly, there has been adrawback in that it takes lots of time to perform erasing in the case ofa small data size and, therefore, the entire writing time becomes longerafter all.

DISCLOSURE OF INVENTION

The present invention has been made to solve the above-mentionedproblems. The present invention is directed to a semiconductor memorycard used by being connected to an access unit. The semiconductor memorycard comprises: a host interface section which sends a control signaland data to the access unit and receives a signal from the access unit;a nonvolatile memory which includes a plurality of nonvolatile memorychips and in which a plurality of continuous sectors is grouped to be ablock as a minimum unit of data erasing; a memory controller whichcontrols erasing, writing, and reading of data with respect to thenonvolatile memory; and a host information memory which temporarilystores a data write start address and a data size value given by theaccess unit. Herein, the memory controller includes a free physical areageneration section which determines whether or not to perform erasing ofinvalid blocks of the nonvolatile memory based on the data write startaddress and the data size value temporarily stored in the hostinformation memory, and simultaneously performs writing of data to onenonvolatile memory chip and erasing of blocks of another nonvolatilememory chip when performing erasing of the invalid blocks.

The present invention is also directed to a semiconductor memory controlapparatus which is used in a semiconductor memory card and is used bybeing connected to a nonvolatile memory which includes a plurality ofnonvolatile memory chips and in which a plurality of continuous sectorsis grouped to be a block as a minimum unit of data erasing. Thesemiconductor memory control apparatus includes: a host interfacesection which sends a control signal and data to an access unit andreceives a signal from the access unit; a memory controller whichcontrols erasing, writing, and reading of data with respect to thenonvolatile memory; and a host information memory which temporarilystores a data write start address and a data size value given by theaccess unit. Herein, the memory controller includes a free physical areageneration section which determines whether or not to perform erasing ofinvalid blocks of the nonvolatile memory based on the data write startaddress and the data size value temporarily stored in the hostinformation memory, and simultaneously performs writing of data to onenonvolatile memory chip and erasing of blocks of another nonvolatilememory chip when performing erasing of the invalid blocks.

The present invention is also directed to a semiconductor memory controlmethod in a semiconductor memory card having a nonvolatile memory whichincludes a plurality of nonvolatile memory chips and in which aplurality of continuous sectors is grouped to be a block as a minimumunit of data erasing. The semiconductor memory control method includesthe steps of: temporarily storing a data write start address and a datasize value given by an access unit in a host information memory;determining whether or not to perform erasing of invalid blocks of thenonvolatile memory based on the data write start address and the datasize value temporarily stored in the host information memory; andsimultaneously performing writing of data to one nonvolatile memory chipand erasing of blocks of another nonvolatile memory chip when performingerasing of the invalid blocks.

According to the present invention, the number of erase blocks isdetermined based on a write start address and a write size obtained fromthe access unit, and the erase block is erased in accordance with datawriting. Consequently, erasing can be performed without exposing theerase time and without lowering the processing performance, and a freeblock can be increased. A high-speed access to a semiconductor memorycard, therefore, can be realized.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is an explanatory diagram showing a semiconductor memory card andan access unit according to Embodiment 1 of the present invention.

FIG. 2 is an explanatory view showing a table of a logical/physicalconversion control section according to Embodiment 1 of the presentinvention.

FIG. 3 is an explanatory view showing a configuration of erase blocksaccording to Embodiment 1 of the present invention.

FIG. 4 is a flowchart showing a data write process in the semiconductormemory card according to Embodiment 1 of the present invention.

FIG. 5 is a flowchart showing processing of subroutine (1) according toEmbodiment 1 of the present invention.

FIG. 6 is a flowchart showing processing of subroutine (2) according toEmbodiment 1 of the present invention.

FIG. 7 is a time chart showing writing of data and an erase process ofthe erase blocks according to Embodiment 1 of the present invention.

FIG. 8 is a time chart showing a write process and an erase process in amemory chip when a memory controller and a nonvolatile memory have acommon bus according to Embodiment 1 of the present invention.

FIG. 9 is an explanatory diagram showing a semiconductor memory card andan access unit according to Embodiment 2 of the present invention.

FIG. 10 is an explanatory view showing a configuration of a nonvolatilememory according to Embodiment 2 of the present invention.

FIG. 11 is a time chart showing a write process at a high speed modeaccording to Embodiment 2 of the present invention.

FIG. 12 is a time chart showing a write process at a low speed modeaccording to Embodiment 2 of the present invention.

FIG. 13 is an explanatory diagram showing a semiconductor memory cardand an access unit according to Embodiment 3 of the present invention.

FIG. 14 is an explanatory view showing a table of a logical/physicalconversion control section according to Embodiment 3 of the presentinvention.

FIG. 15 is an explanatory view showing a defragmentation processaccording to Embodiment 3 of the present invention.

FIG. 16 is a flowchart showing the defragmentation process according toEmbodiment 3 of the present invention.

FIG. 17 is an explanatory diagram showing a semiconductor memory cardand an access unit according to Embodiment 4 of the present invention.

FIG. 18 is an explanatory view showing a configuration of a nonvolatilememory according to Embodiment 4 of the present invention.

FIG. 19 is a time chart showing a recording process of data in aconventional example.

FIG. 20 is a time chart showing a recording process of data according toEmbodiment 4 of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of a semiconductor memory card, a semiconductormemory control apparatus, and a semiconductor memory control methodaccording to the present invention will be described with reference tothe drawings.

Embodiment 1

FIG. 1 is a block diagram showing a semiconductor memory card and anaccess unit according to Embodiment 1 of the present invention. In FIG.1, an access unit 100 is connected to a semiconductor memory card 111.The semiconductor memory card 111 includes a host interface (I/F)section 112, a CPU 113, a RAM 114, a ROM 115, a memory controller 116, anonvolatile memory 117, and a host information memory 118. The hostinterface section 112 is an interface for sending/receiving controlsignals and data to/from the access unit 100. The ROM 115 stores aprogram for controlling the semiconductor memory card 111. The programruns on the CPU 113 using the RAM 114 as a temporary storage area. Thememory controller 116 is an element for controlling the nonvolatilememory 117. The nonvolatile memory 117 is a data storage area in thesemiconductor memory card 111. The memory controller 116 includes alogical/physical conversion control section 120, a free physical areageneration section 121, and a nonvolatile memory access section 123. Thelogical/physical conversion control section 120, as will be describedlater, includes a logical/physical conversion table 131 and an entrytable 132. Further, the free physical area generation section 121determines whether or not to erase invalid blocks of the nonvolatilememory 117 based on a data write start address and a data size sent fromthe access unit 100, and simultaneously performs writing of data anderasing when performing erase of the invalid blocks. The nonvolatilememory access section 123 performs writing, reading, and erasing of databy the memory controller 116 directly accessing the nonvolatile memory117. In addition, all blocks except for the nonvolatile memory 117 inthe semiconductor memory card constitute a semiconductor memory controlapparatus.

The nonvolatile memory 117 is composed of memory chips A and B of twoflash memories and each nonvolatile memory chip has a data capacity of16 MB, for example. The nonvolatile memory 117, as will be describedlater, is composed of an address management area and a data area. Twomemory chips A and B are connected to the memory controller 116 withindependent bidirectional buses.

Further, the host information memory 118 temporarily stores the datawrite start sector address SA at a sector unit given by the access unit100 and a write size L at the sector unit.

FIG. 2 is an explanatory view showing the logical/physical conversioncontrol section 120. The logical/physical conversion control section 120is composed of the logical/physical conversion table 131 and the entrytable 132. The logical/physical conversion table 131 is a table showingconversion from a logical sector address LSA designated by the accessunit 100 to a physical sector address PSA. The nonvolatile memory 117has a space of 2N sectors as a logical space, and logical sectoraddresses of the memory chip A and memory chip B are logicallycontinuous. In the logical/physical conversion table 131, the first halfpart, that is, logical sector addresses 0 to N−1, is a table areacorresponding to the nonvolatile memory chip A, and the last half part,that is, logical sector addresses N to 2N−1, is a table areacorresponding to the nonvolatile memory chip B. In FIG. 2, assumed thateach logical sector has a user data area of 512 B, when the memory chipsA and B each have a data capacity of 16 MB, the logical sector address Nshown in FIG. 2 becomes 2¹⁵. Here, one physical block is formed by 32sectors. Accordingly, since each physical block has a capacity of 16 KBand this physical block is also a unit which can be selectively erased,it is called an erase block.

The entry table 132 is a table showing states of respective physicalblocks of physical block addresses PBA 0 to 2M−1, and each physicalblock is indicated by 2-bit data. Here, 00 denotes a valid block inwhich valid data is recorded, 11 denotes an invalid block that datarecorded is invalid data, 10 denotes a defective block, and 01 denotesan erased block. In also the entry table 132, the first half part, thatis, the physical block addresses 0 to M−1, is a table area correspondingto the nonvolatile memory chip A, and the last half part, that is, thephysical block addresses M to 2M−1, is a table area corresponding to thenonvolatile memory chip B. These two tables 131 and 132 are respectivelyrecorded in volatile memories such as RAM.

FIG. 3 is an explanatory view showing a configuration of erase blocksarranged in respective memory chips A and B. One erase block is composedof pan 32 sectors. Each sector area has an area of 528 bytes, which iscomposed of a data area of 512 bytes for writing so-called user data anda management region (MR) of 16 bytes for writing address managementinformation. The address management information includes a flag or thelike which indicates that a corresponding logical address and datastored in the data area are valid, invalid, or a defective block. Then,during initialization immediately after power on, the CPU 113 readsinformation stored in the management region MR of each erase block ofthe memory chips A and B to produce the logical/physical conversiontable 131 and entry table 132 of FIG. 2 in the RAM in thelogical/physical conversion control section 120.

The operation in writing period of the thus-configured semiconductormemory card will be described by using flowcharts of FIGS. 4 to 6 andtime charts of FIGS. 7 and 8. When writing, the access unit 100 firsttransfers the data write start sector address SA and the write size L tothe semiconductor memory card 111 in addition to a write command. Thestart sector address SA and the write size L are temporarily stored inthe host information memory 118. The memory controller 116, based on thestart sector address SA and the write size L temporarily stored in thehost information memory 118 and parameters (sector address N) beingindicative of interface between the first half area and second half areaof the nonvolatile memory 117, determines whether or not SA is less thanN (step S101). Further, if SA is less than N, it is determined whetheror not SA+L exceeds N (step S102). Accordingly, it is determined whetheror not writing should be performed only in the first half area (memorychip A), only in the last half area (memory chip B), or in both areas.

If writing is performed only in the first half area, the processing goesto step S103 to set a pointer m to L. The pointer m denotes a write sizein each memory chip. Then, the processing of subroutine (1) is performed(step S104), and then, completed. Further, in step S101, if N is notless than SA, writing is performed only in the last half area, thereforethe pointer m is set to L in step S105 and the processing of subroutine(2) is performed in step S106 (step S106), and then, completed. Inaddition, if writing is performed from the first half area to the lasthalf area, that is, if writing is performed in two memory chips A and B,the pointer m is set to N-SA in step S107 to perform write processing inthe memory chip A by the subroutine (1) (step S108). After that, in step109, the pointer m is set to L-m to perform write processing in thememory chip B by the subroutine (2) in step S110 (step S111).

FIG. 5 is a flowchart showing processing of the subroutine (1). In thisflowchart, when the operation is started, it is first checked whether ornot m×512 B exceeds 4 KB in step S111. In Embodiment 1, a write time of2 mSec is needed when the write data size is 4 KB. The free physicalarea generation section 121 determines, whether or not a memory chip(here, the memory chip B) other than a memory chip to be written iserased, by a write data size that is 8 times a 512 B unit, that is, notless than 4 KB or not. An erase command is issued when performing erase.If this value exceeds 4 KB in step S111, calculation of (m×512 B)/4 KBis performed in step S112. Here, n is set as an integer number of thequotient. Then, the processing goes to step S113 to write data, which issent to a free block of the memory chip A, with address managementinformation. Further, n invalid blocks of the memory chip B aresimultaneously erased. It is determined whether or not they are invalidblocks depending on whether or not 11 is recorded in the entry table132. After performing erase, the entry table is updated as 01, that is,an erased block, for the block. All invalid blocks are erased if thenumber of invalid blocks is not more than n, and erasing is not neededif there are no invalid blocks. Further, if the write data size is lessthan 4 KB in step S111, writing is performed only in a free block of thememory chip A to complete the processing.

Next, FIG. 6 is a flowchart showing the subroutine (2). In thisflowchart, when the operation is started, it is first checked whether ornot m×512 B exceeds 4 KB in step S121. In Embodiment 1, an example whicha write time of 2 mSec is needed when the write data size is 4 KB isshown, and the free physical area generation section 121 determines,whether or not a memory chip (here, the memory chip A) other than amemory chip to be written is erased, by a write data size that is 8times a 512 B unit, that is, not less than 4 KB or not. An erase commandis issued when performing erase. If this value exceeds 4 KB in stepS121, calculation of (m×512 B)/4 KB is performed in step S122. Here, nis set as an integer number of the quotient. Then, the processing goesto step S123 to write data, which is sent to a free block of the memorychip B, with address management information. Further, n invalid blocksof the memory chip A are simultaneously erased. It is determined whetheror not they are invalid blocks depending on whether or not 11 isrecorded in the entry table 132. After performing erase, the entry tableis updated as 01, that is, an erased block, for the block. All invalidblocks are erased if the number of invalid blocks is not more than n,and erasing is not needed if there are no invalid blocks. Further, ifthe write data size is not more than 4 KB in step S121, writing isperformed only in a free block of the memory chip B to complete theprocessing.

Next, writing in the memory chip A and erase processing in the memorychip B in step S113 will be described by using a time chart. FIG. 7shows a time chart when the write size is 4 KB in the case of writingonly in the first half area (memory chip A). The upper part of FIG. 7shows access to the memory chip A. An issue period of a write command WCis a period for transferring write instruction to the nonvolatile memorychip A and an address to be written. A data transfer (DATA) period is aperiod for transferring write data to the memory chip A. Further, aprogram busy period (BUSY) is a period for actually writing write datain the memory chip A. Actually, a write command is issued by thenonvolatile memory access section 123. After that, in transferring data,write data of 512 B for one sector and data of 16 B for a managementarea corresponding to the write data, that is, a data transfer of 528 Bis performed. This period is approximately 50 μs. A busy flag (BUSY) isthen flagged at write time. This period is approximately 200 μs. Whenwriting (W1) in the first sector is completed in this way, writing bysimilar processing is repeated in the next sector. By writing data for 8sectors in this way, one physical block, that is, data for 4 KB can bewritten. The data write time required for this 4 KB is 250×8 (μs), thatis, approximately 2 ms.

On the other hand, in synchronization with this, erase processingrequiring almost the same time is performed in the memory chip B. Ablock to be erased in the memory chip B is a physical block shown as aninvalid block (11 in binary) in the entry table 132. An erase command ECis issued to this physical block. By doing this, an erase busy signal(BUSY) can be obtained in the erase period, and erasing can be performedduring this time.

Here, when a NAND type flash memory or the like is used as thenonvolatile memory, the erase busy time is longer (for example, 2 mSec)compared to the program busy time (200 μs).

By the above-mentioned processing, when a write size in the memory chipA is not less than 4 KB, writing process is simultaneously performedwith erasing in the memory chip B, thereby permitting the entireprocessing performance to be rationalized because of not exposing anerase time. By further calculating the number of erase blockscorresponding to the write size L, processing performance is notdegraded and as many as possible of sectors can be erased.

Further, FIG. 7 shows an example in which writing in the memory chip Aand erasing in the memory chip B are simultaneously performed; however,as shown in step S123 of a flowchart in FIG. 6, in the case of writingin the memory chip B and erasing in the memory chip A, the sameoperations are performed although the memory chips A and B are merelyreversed. In addition, in the case of writing in both memory chips A andB, these processing are sequentially performed.

Further, in this embodiment, the memory chips A and B of the nonvolatilememory 117 are connected to the memory controller 116 with independentbuses, but they may be commonly connected with one bus. In that case,however, the free physical area generation section 121 staggers issuingtiming between the write command WC and the data transfer period, andthe erase command temporarily so that bus conflict does not occurbetween the write command and the erase command of FIG. 7. That is, asshown in FIG. 8, the erase command EC is issued after the write commandissue period WC using a bus and the data transfer period (DATA). Then,if the BUSY state is completed after issuing the erase command, thewrite command of the next sector and data transfer following this writecommand are performed. This enables a plurality of memory chips and thememory controller to be commonly connected with one bus.

Further, in this embodiment, in the case of requiring a write time whichcorresponds to the erase time of the erase block, erasing and writingare performed in parallel. Values shown here are one example and thesevalues can be appropriately selected according to the write time and theerase time.

In addition, the logical/physical conversion table shown in FIG. 2 maybe a conversion table for converting at a block unit. Further, it may beconverted at a unit which a plurality of erase blocks serves as a group.Furthermore, in this embodiment, two memory chips are used as thenonvolatile memory; however, it may be constituted by using a pluralityof any memory chip.

Embodiment 2

FIG. 9 is a block diagram showing a semiconductor memory card accordingto Embodiment 2 of the present invention. In this figure, an access unit100 is connected to a semiconductor memory card 111. The semiconductormemory card 111 includes a host interface (I/F) section 112, a CPU 113,a RAM 114, a ROM 115, a memory controller 141, a nonvolatile memory 117,and a host information memory 142. The host interface section 112 is aninterface for sending/receiving control signals and data to/from theaccess unit 100. The ROM 115 stores a program for controlling thesemiconductor memory card 111. The program runs on the CPU 113 using theRAM 114 as a temporary storage area. The memory controller 116 is anelement for controlling the nonvolatile memory 117. The nonvolatilememory 117 is a data storage area in the semiconductor memory card 111.The memory controller 141 includes a logical/physical conversion controlsection 143 and a nonvolatile memory access section 144. Thelogical/physical conversion control section 143 includes alogical/physical conversion table and an entry table. The nonvolatilememory access section 144 performs writing, reading, and erasing of databy directly accessing the nonvolatile memory 117 from the memorycontroller 141.

The nonvolatile memory 117 is composed of memory chips A and B of twoflash memories and each nonvolatile memory chip has a data capacity of16 MB, for example. The nonvolatile memory 117, as will be describedlater, is composed of an address management area and a data area. Twomemory chips A and B are connected to the memory controller 141 withindependent bidirectional buses No. 0 and No. 1

The host information memory 142 stores an access speed transferred bythe access unit 100, and either state of a high speed mode or a lowspeed mode is stored. When the high speed mode is set, since thenonvolatile memory access section 144 permits access with a large peakcurrent, access at high speed is performed upon accessing thenonvolatile memory 117. Further, when the low speed mode is set, uponaccessing the nonvolatile memory 117, it is controlled so that the loadon the power supply is alleviated by decreasing the peak current.

FIG. 10 is an explanatory diagram showing an internal configuration ofmemory chips A and B. Each of the memory chips A and B in thenonvolatile memory 117 is respectively divided into four banks, bank B0to bank B3. Bank B0 to bank B3 perform writing simultaneously at eachpage unit. Each erase block EB (4 KB=4224 B) is composed of two pages,that is, page 0 and page 1. All eight erase blocks composed by each oneerase block in every bank of the memory chips A and B constitute as alogical section LS. The entire nonvolatile memory 117 is composed by 256sections, LS0 to LS255.

The operation of the semiconductor memory card and the access unit asconfigured above will be described with reference to mainly FIGS. 10 and11. First, when initializing after powering on the access unit 100, orwhen switching on the access unit 100, the speed mode is transferred tobe stored in the host information memory 142. The nonvolatile memoryaccess section 144 determines an access mode with reference to the speedmode stored in the host information memory 142.

Next, the case of the high speed mode will be described by using FIG.11. When writing at the high speed mode is performed, write data A, B,C, D, . . . are continuously transferred from the access unit 100 viathe host interface section 112 as shown in FIG. 11. Here, logicaladdresses of the write data are continuous addresses. Thethus-transferred dada are first stored in buffer. The addresses areconverted to physical addresses by the logical/physical conversioncontrol section 143. The data and addresses are written in the memorychip A via the bus No. 0. Here, WC denotes a write command. Further, T1denotes a data transfer period and T2 denotes a program busy time inwhich write processing in the memory chip A is actually performed. Whendata transfer of the bus No. 0 is completed, followed by the writecommand to the bus No. 1, data transfer of the data B is subsequentlyperformed in the period of T1. Writing of the data is performed in thememory chip B in the period of T2. During the writing, when writeprocessing is completed in the memory chip A, write command, datatransfer of the data C, and writing are performed from the bus No. 0.Further, writing in the memory chip B is completed, transfer of writecommand and the data D, and data writing processing are performed. Asdescribe above, the write time of the data A and C and the write time ofthe data B and D are overlapped as shown in FIG. 11, but writingprocessing with high speed is performed by writing in parallel.

On the other hand, the case that the speed mode set for the hostinformation memory 142 is a low speed mode will be described by usingFIG. 12. An actual write period of write data A, B, C, D, . . . , thatis, a program busy period is a period that consumes much currentcompared to data transfer. In the low speed mode, writing is controlledso that the program busy time is not overlapped temporally. Morespecifically, the write command WC is issued for the bus No. 0, and ifthe data A is transferred, writing in the memory chip A is performed tobecome the program busy (BUSY) during this period. The nonvolatilememory access section 144 feedbacks a card busy signal to the accessunit 100 to stop data transfer until the write processing is completedand release of the program busy signal (BUSY) of the memory chip A to bewritten is informed to the nonvolatile memory access section 144. Afterthat, when the stop is released, the data B is subsequently transferredfrom the access unit 100. After this, the write command WC is issued tothe bus No. 1 to perform data transfer of the data B. Consequently, itbecomes the program busy (BUSY) when writing by the memory chip. Duringthis time, the data transfer is stopped by the access unit 100. If thewriting is completed, the next data C is transferred to repeat the sameprocessing. By such a bidirectional control, program busy period whichconsumes much current is dispersed to suppress the peak current.

Consequently, when the access unit 100 in which withstanding currentvalue of a power supply circuit is low is used, the access unit 100 setsthe host information memory 142 to be the low speed mode in order toselect the low speed mode. On the other hand, when high speed access isrequired in the case of using the access unit 100 in which withstandingcurrent value of the power supply circuit is high, the access unit 100sets host information memory 142 to be the high speed mode. Thenonvolatile memory access section 144 selects the access mode shown inFIG. 11 or 12 to perform writing control corresponding to each mode.

Further, this embodiment switches between the high speed mode whichpermits overlap of data write and the low speed mode which does notpermit the overlap by using two memory chips A and B. In the case ofmany further memory chips, four memory chips, for example, it may beswitched between the low speed mode which permits overlapped writing oftwo memory chips and the high speed mode which can simultaneouslyperform writing in all memory chips. Further, only writing in eithermemory chip may be permitted at low speed mode, and overlapped writingin two or more memory chips may be permitted at high speed mode.

The semiconductor memory card according to this embodiment is asemiconductor memory card used by being connected to an access unit,comprises:

a host interface section which sends a control signal and data to theaccess unit and receives a signal from the access unit;

a nonvolatile memory which includes a plurality of nonvolatile memorychips and in which a plurality of continuous sectors is grouped to be ablock as a minimum unit of data erasing;

a memory controller which is connected to each of the plurality ofnonvolatile memory chips with respectively independent bidirectionalbuses and controls erasing, writing, and reading of data; and

a host information memory which temporarily stores a write speed modegiven by the access unit, wherein

the memory controller includes a nonvolatile memory access section whichperforms writing with respect to the plurality of nonvolatile memorychips with controlling write timing to each of the plurality ofnonvolatile memories depending on a speed mode stored in the hostinformation memory.

Here, writing is performed in parallel with respect to the plurality ofnonvolatile memory chips when the write speed mode stored in the hostinformation memory is a high speed mode, and writing is sequentiallyperformed with respect to the plurality of nonvolatile memory chips whenthe write speed mode stored in the host information memory is a lowspeed mode.

Further, the semiconductor memory control method according to thisembodiment is a semiconductor memory control method in a semiconductormemory card having a nonvolatile memory which includes a plurality ofnonvolatile memory chips and in which a plurality of continuous sectorsis grouped to be a block as a minimum unit of data erasing, the methodincluding the step of:

performing writing with respect to the plurality of nonvolatile memorychips with controlling write timing to each of the plurality ofnonvolatile memories depending on the speed mode stored in the hostinformation memory.

Embodiment 3

Next, Embodiment 3 of the present invention will be described. FIG. 13is a block diagram showing a semiconductor memory card according to thisembodiment. In FIG. 13, an access unit 100 is connected to asemiconductor memory card 111. The semiconductor memory card 111includes a host interface (I/F) section 112, a CPU 113, a RAM 114, a ROM115, a memory controller 151, a nonvolatile memory 117, and a hostinformation memory 155. The host interface section 112 is an interfacefor sending/receiving control signals and data to/from the access unit100. The ROM 115 stores a program for controlling the semiconductormemory card 111. The program runs on the CPU 113 using the RAM 114 as atemporary storage area. The memory controller 151 is an element forcontrolling the nonvolatile memory 117. The nonvolatile memory 117 is adata storage area in the semiconductor memory card 111. The memorycontroller 151 includes a logical/physical conversion control section152, a free physical area generation section 153, and a nonvolatilememory access section 154. The logical/physical conversion controlsection 152, as will be described later, includes a logical/physicalconversion table 156 and an entry table 157. Further, the free physicalarea generation section 153 organizes a recorded state in thenonvolatile memory 117 to increase a free block (erased block) and to bein a writable state at any time without erasing before writing. Thenonvolatile memory 117 may be one memory chip or may be those using aplurality of nonvolatile memories. In addition, an erase block in thenonvolatile memory 117 is the same as FIG. 3 of Embodiment 1.

Here, at the time that data is written in the sector not less than apredetermined threshold Th1 at each erase block unit, the free physicalarea generation section 153 sets the erase block as a defragmentationobject block to register it in the entry table of the logical/physicalconversion control section 152 to be described later. Further, as willbe described later, the free block in the entry table is counted and adefragmentation request signal is sent to the access unit 100 when thecounted value becomes not more than a predetermined threshold Th2.

FIG. 14 is an explanatory view showing a logical/physical conversioncontrol section 152. The logical/physical conversion control section 152is a table which manages conversion processing from a logical sectoraddress LSA designated by the access unit 100 to a physical sectoraddress PSA and states of respective physical blocks. The table iscomposed of the logical/physical conversion table 156 which converts thelogical sector address LSA to the physical sector address PSA and theentry table 157. The entry table 157 stores 3-bit information whichshows a state of each physical block corresponding to respective blockaddresses PBA0 to M−1. Here, 000 denotes a valid block, 011 denotes aninvalid block, 010 denotes a defective block, 001 denotes a free block,that is, an erased block, and 100 denotes an objective block whichdefragmentation is to be made. These two tables are stored in a volatilememory such as RAM. During initialization immediately after power on,the CPU 113 reads information stored in the management area of eacherase block of the nonvolatile memory 117 to produce thelogical/physical conversion table 156 and the entry table 157 on the RAMin the logical/physical conversion control section 152.

The operation of the semiconductor memory card and the access unit asconfigured above will be described with mainly reference to FIGS. 15 and16. While the access unit 100 performs processing such as writing in thesemiconductor memory card, the number of free blocks in the nonvolatilememory 117 gradually decreases. Here, in Embodiment 3, as in Embodiment2, each sector (page) in the erase block is not written in logicalorder, but logical sectors transferred by the access unit 100 arewritten in ascending order of the erase blocks regardless of theirlogical sector address. More specifically, as shown in FIG. 15, when theaccess unit 100 issues commands for writing in the logical sectors LS4,LS0, LS0, LS1, LS3, . . . , writing is performed in ascending order atthe position of the sector Nos. 0, 1, 2, 3, . . . of the erase block 1.Further, N is a flag showing new flag information, 0 is a flag showingold flag information.

FIG. 16 is a flowchart showing processing of the semiconductor memorycard. When the operation starts, it is checked whether or not there isan access request in step S301 first, and if there is no access request,it is checked whether or not there is a defragmentation instruction(step S302). If there is the access request, card access is performed instep S303. Then, it is checked whether or not the valid sector writtenin step S303 in the erase block of the nonvolatile memory exceeds thethreshold Th1. If it is not more than the threshold Th1, similarprocessing is repeated by getting back to the loop in steps S301 andS302. When the card access is forwarded and at the time that the sector,which exceeds the threshold Th1, is written in the erase block, the freephysical area generation section 153 registers the erase block as thedefragmentation object block in the entry table 157 of FIG. 14 (stepS305). Then, the data of logical sectors, subsequently transferred bythe access unit 100, is written searching another free block (erasedblock) from the entry table 157. By continuing this process, the numberof the free blocks in the entry table is gradually decreased, on thecontrary, the number of the defragmentation object blocks is increased.The free physical area generation section 153 sets the erase blocks asthe defragmentation object blocks in step S305, after that, counts thenumber of free blocks going to step S306 to check whether or not it isnot more than the threshold Th2. If the number of the free blocksexceeds the threshold Th2, similar processing is repeated getting backto the loop in steps S301 and S302. If the number of the free blocks isnot more than the threshold, the number of the defragmentation objectblocks is ordinarily considered to be many, and therefore, thedefragmentation request signal is sent to the access unit 100 going tostep S307. Further, in step S306, the number of the defragmentationobject blocks may be counted instead of the number of the free blocks.In addition, an access count value may be sent to the access unit 100 inplace of the defragmentation request signal in step S307.

Upon receipt of the defragmentation request signal, the access unit 100may immediately transfer a defragmentation instruction signal to thesemiconductor memory card 111. Further, when obtaining theabove-mentioned count value, based on the count value, thedefragmentation instruction signal may be issued corresponding tosubsequently transferring data capacity after assessing a transferperiod of the defragmentation instruction signal. When the memory cardreceives the defragmentation request signal from the access unit,processing goes to step S308 from step S302 to temporarily store thedefragmentation instruction signal transferred by the access unit 100 tothe host information memory 155. Then, the free physical area generationsection 153 refers to this and issues an instruction of defragmentationprocessing to the nonvolatile memory access section 154.

For example, in FIG. 15, erase blocks EB1 and EB5 serve as the eraseblocks registered as the defragmentation object blocks. In this case,instruction of reading/writing is issued to the nonvolatile memoryaccess section 154 so that merge processing is performed in the freeerase block 9 in the order of the logical sectors by seeing each sectornumber (only sector in which a new flag N is marked) of the erase blocksEB1 and EB5. In accordance with the instruction, as shown in FIG. 15,the nonvolatile memory access section 154 copies in the free erase block9 from the logical sectors in which the new flag N is flagged in theerase blocks EB1 and EB5. After that, the erase blocks EB1 and EB5 areregistered in the entry table 157 as invalid blocks. This performsdefragmentation according to the instruction by the access unit, wherebydefragmentation can be performed, when necessary, without lowering speedcompared to the case that the semiconductor memory card performsdefragmentation without instruction by the access unit.

Further, the logical/physical conversion table and the entry table mayuse volatile reading/writing memories other than RAM if they performaccess in a comparatively high speed.

Here, the semiconductor memory card according to this embodiment is asemiconductor memory card used by being connected to an access unit. Thesemiconductor memory card comprises: a host interface section whichsends a control signal and data to the access unit and receives a signalfrom the access unit; a nonvolatile memory which includes a plurality ofnonvolatile memory chips and in which a plurality of continuous sectorsis grouped to be a block as a minimum unit of data erasing; a memorycontroller which controls erasing, writing, and reading of data withrespect to the nonvolatile memory; and a host information memory whichtemporarily stores a defragmentation instruction signal given by theaccess unit. Herein, the memory controller includes a free physical areageneration section which detects a remaining amount of erased blocks ofthe nonvolatile memory, issues a defragmentation request signal to theaccess unit when the number of erased blocks is a predetermined numberor less, and executes defragmentation when the defragmentationinstruction signal is temporarily stored in the host information memory.

Further, the semiconductor memory control method according to thisembodiment is a semiconductor memory control method in a semiconductormemory card having a nonvolatile memory which includes a plurality ofnonvolatile memory chips and in which a plurality of continuous sectorsis grouped to be a block as a minimum unit of data erasing. Thesemiconductor memory control method comprises the steps of: temporarilystoring a defragmentation instruction signal given by an access unit ina host information memory; detecting a remaining amount of erased blocksof the nonvolatile memory; issuing a defragmentation request signal tothe access unit when the number of erased blocks is a predeterminednumber or less; and executing defragmentation when the defragmentationinstruction signal is temporarily stored in the host information memory.

Embodiment 4

FIG. 17 is a block diagram showing an access unit and a semiconductormemory card according to Embodiment 4 of the present invention. In FIG.17, an access unit 100 is connected to a semiconductor memory card 111.The semiconductor memory card 111 includes a host interface (I/F)section 112, a CPU 113, a RAM 114, a ROM 115, a memory controller 161, anonvolatile memory 164, and a host information memory 165. The hostinterface section 112 is an interface for sending/receiving controlsignals and data to/from the access unit 100. The ROM 115 stores aprogram for controlling the semiconductor memory card 111. The programoperates on the CPU 113 using the RAM 114 as a temporary storage area.The memory controller 161 is an element for controlling the nonvolatilememory 164. The nonvolatile memory 164 is a data storage area in thesemiconductor memory card 111. The memory controller 164 includes alogical/physical conversion control section 162 and a nonvolatile memoryaccess section 163. The nonvolatile memory access section 163 performswriting, reading, and erasing of data by directly accessing thenonvolatile memory 164 from the memory controller 161.

Further, the host information memory 165 temporarily stores anallocation table update instruction signal from the access unit 100.

FIG. 18 is an explanatory view showing an internal configuration of anonvolatile memory 164. An erase block and page specifications of thenonvolatile memory 164 are the same as those of the nonvolatile memorychip of Embodiment 2. The nonvolatile memory 164 is different fromEmbodiments 1 to 3 and address management information is stored in anallocation table (AT) area of the nonvolatile memory 164 in a formattype of the logical/physical conversion table and the entry table. Here,the allocation table (AT) denotes a table which the memory controller161 controls the nonvolatile memory 164. The allocation table area (ATarea) is to collectively record AT which is management information inanother area different from the data area. If the number of the eraseblocks existing in the nonvolatile memory 164 is very large, when themethod of producing the logical/physical conversion table and an entrytable on the RAM is adopted, based on the management information of themanagement area in each erase block at initialization as in Embodiments1 to 3, it takes comparatively much time. Consequently, in the case ofusing the nonvolatile memory whose number of the erase blocks of islarge, an AT management system (hereinafter, referred to as acentralized store system) in which management information is intensivelystored in the specified AT area of the nonvolatile memory 164, isadopted in order to shorten the initialization time.

The logical/physical conversion control section 162 includes thelogical/physical conversion table and the entry table. Both are storedin volatile memories such as RAM. During initialization immediatelyafter power on, the CPU 113 reads the allocation table on the AT area ofthe nonvolatile memory 164 to produce the logical/physical conversiontable and the entry table on the RAM in the logical/physical conversioncontrol section 162. Reading of data from the AT area, that is, AT readmay be only during initialization when AT manages all data areas.

The operation of the semiconductor memory card and the access unit asconfigured above will be described with mainly reference to FIGS. 18 to20. FIG. 19 is an explanatory view showing an access form of theconventional nonvolatile memory access section. FIG. 20 is anexplanatory view showing an access mode of the nonvolatile memory accesssection 163. The conventional semiconductor memory card simultaneouslyupdates the table of the logical/physical conversion control section 162every writing data by the access unit 100. Accordingly, updated table ofthe logical/physical conversion control section 162 need to be writtenback to the nonvolatile memory 164. FIG. 19 shows processing of datawrite information. Data write denotes a data write period, and AT writedenotes processing in which the updated table of the logical/physicalconversion control section 162 is written back to the AT area in thenonvolatile memory 164.

The processing performance is degraded by temporal overhead which isrequired for this AT write. More particularly, when data write capacityis small, proportion of the AT write time to the entire processing time(data write time+AT write time) becomes comparatively large to have aproblem.

In the system that the access unit 100 continuously writes user datahaving in the order of several hundreds kilobytes in size, for example,and a FAT update on the side of the access unit 100 also updates in theorder of several hundreds kilobytes, AT may update corresponding to itscycle. The reason is that when a file allocation table (hereinafter,referred to as FAT) is updated and power-off or the like occurs beforethe completion of writing in the nonvolatile memory 164, FAT is notupdated, and therefore, AT also need not update. Meanwhile, it may besaid that it is more reasonable if the FAT update matches the AT update.A span of the FAT update differs according to usage of the access unit100. Accordingly, in order to optimize processing performancecorresponding to the usage, timing of the AT update may be controlled bythe access unit 100 to transfer an AT update instruction signal.Consequently, in Embodiment 4, the AT update instruction signal, whichthe access unit 100 instructs the AT update, is used.

In this embodiment, as shown in FIG. 20, writing in the FAT is completedafter writing a plurality of data, and then, the AT update instructionsignal is supplied to the semiconductor memory card by the access unit100, that is the host. The AT update instruction signal is first storedin the host information memory 165. The nonvolatile memory accesssection 163 writes information of the logical/physical conversion tableand conversion table in the updated logical/physical conversion controlsection 162 as AT in the AT area of the nonvolatile memory 164.

As with the above, when also a plurality of data are erased, writing inthe FAT is completed, and then, the AT update instruction signal issupplied to the semiconductor memory card by the access unit 100, thatis the host. The AT update instruction signal is first stored in thehost information memory 165. The nonvolatile memory access section 163writes information of the logical/physical conversion table andconversion table in the updated logical/physical conversion controlsection 162 as AT in the AT area of the nonvolatile memory 164.Consequently, temporal overhead when writing in AT can be reduced andprocessing performance can be improved.

Here, the semiconductor memory card according to this embodiment is asemiconductor memory card used by being connected to an access unit. Thesemiconductor memory card comprises: a host interface section whichsends a control signal and data to the access unit and receives a signalfrom the access unit; a nonvolatile memory in which a plurality ofcontinuous sectors is grouped to be a block as a minimum unit of dataerasing, and in which an address management information area and a userdata area are stored in respective different blocks; a memory controllerwhich has a volatile memory holding address management information,performs erasing, writing, and reading of data, and updates the volatilememory in every erasing, and writing of data; and a host informationmemory which temporarily stores address management information updatesignal transferred from the access unit. Herein, the memory controllerincludes a nonvolatile memory access section which writes datatransferred when a write command and data are given by the access unitto the nonvolatile memory, erases blocks designated when an erasecommand is given, and writes address management information held in thevolatile memory of the memory controller to the address managementinformation area of the nonvolatile memory when the address managementinformation update signal is held in the host information memory.

Further, the semiconductor memory control method according to thisembodiment is a semiconductor memory control method in a semiconductormemory card having a nonvolatile memory in which a plurality ofcontinuous sectors is grouped to be a block as a minimum unit of dataerasing, and in which an address management information area and a userdata area are stored in respective different blocks. The semiconductormemory control method includes the steps of: updating a volatile memory,which is provided for holding address management information, in everyerasing, and writing of data with respect to the nonvolatile memory;temporarily storing an address management information update signaltransferred from the access unit in a host information memory; writingdata transferred when a write command and data are given by the accessunit to the nonvolatile memory; erasing blocks designated when an erasecommand is given; and writing the address management information held inthe volatile memory of the memory controller to the address managementinformation area of the nonvolatile memory when the address managementinformation update signal is held in the host information memory.

INDUSTRIAL APPLICABILITY

A semiconductor memory card and a semiconductor memory control apparatusrelated to the present invention can realize high speed access withrespect to the semiconductor memory card by optimizing processing oneither side or on both sides of an access unit and the semiconductormemory card. Such a semiconductor memory card, an access unit, or amethod can be applied to digital AV apparatuses, mobile telephoneterminals, digital cameras, PCs, and the like in which a semiconductormemory card is used as a recording medium, and more particularly, cansuitably function in the case for use in recording media and apparatusesthat record high quality AV data having a high transfer rate.

1. A semiconductor memory card used by being connected to an accessunit, comprising: a host interface section which sends a control signaland data to said access unit and receives a signal from said accessunit; a nonvolatile memory which includes a plurality of nonvolatilememory chips and in which a plurality of continuous sectors is groupedto be a block as a minimum unit of data erasing; a memory controllerwhich is connected to each of said plurality of nonvolatile memory chipswith a bidirectional bus and controls erasing, writing, and reading ofdata; and a host information memory which temporarily stores a writespeed mode given by said access unit, wherein said memory controllerperforms, in parallel, writing with respect to said plurality ofnonvolatile memory chips when the write speed mode stored in said hostinformation memory is a high speed mode, and sequentially performswriting with respect to said plurality of nonvolatile memory chips whenthe write speed mode stored in said host information memory is a lowspeed mode.
 2. A semiconductor memory apparatus used by being connectedto an access unit, comprising: a host interface section which sends acontrol signal and data to said access unit and receives a signal fromsaid access unit; a nonvolatile memory which includes a plurality ofnonvolatile memory chips and in which a plurality of continuous sectorsis grouped to be a block as a minimum unit of data erasing; a memorycontroller which is connected to each of said plurality of nonvolatilememory chips with a bidirectional bus and controls erasing, writing, andreading of data; and a host information memory which temporarily storesa write speed mode given by said access unit, wherein said memorycontroller performs, in parallel, writing with respect to said pluralityof nonvolatile memory chips when the write speed mode stored in saidhost information memory is a high speed mode, and sequentially performswriting with respect to said plurality of nonvolatile memory chips whenthe write speed mode stored in said host information memory is at a lowspeed mode.
 3. A semiconductor memory control method in a semiconductormemory card having a nonvolatile memory which includes a plurality ofnonvolatile memory chips and in which a plurality of continuous sectorsis grouped to be a block as a minimum unit of data erasing and a hostinformation memory for temporarily storing a write speed mode given byan access unit, said semiconductor memory control method comprising thesteps of: performing, in parallel, writing with respect to saidplurality of nonvolatile memory chips when the write speed mode storedin said host information memory is a high speed mode, and sequentiallyperforming writing with respect to said plurality of nonvolatile memorychips when the write speed mode stored in said host information memoryis a low speed mode.